Recent improvements in their spatial and data resolution capabilities have made digital image processing systems attractive for a variety of image-processing (e.g. recording and reproduction) applications. In still image photography, for example, when an image (such as that captured on photographic film or by a high resolution digital camera) has been digitized and stored in an attendant digital data base or framestore, it is readily optimized for reproduction by means of image processing software and a variety of reproduction devices having differing spatial resolutions.
Such a digital image processing system is diagrammatically illustrated in FIG. 1 as comprising a digital image data source, such as a high resolution opto-electronic scanner 12, the output of which is coupled to a host digitized image processor (host computer) 14. In the exemplary system depicted in FIG. 1, scanner 12 may contain a very high resolution sensor pixel array (e.g. a 4096.times.3072 pixel matrix) capable of generating high spatial density-representative output signals which, when converted into digital format, yield `digitized` image files, from which high quality hard copy prints, such as those provided by a laser printer, may be obtained. Namely, the imagery data source (here scanner 12) outputs digitally encoded imagery data, or a `digitized` image. This digital image is supplied in the form of an imaging pixel array-representative bit map, resolved to a prescribed code width (e.g. twelve bits per pixel), to a host processor 14. Host processor 14 typically contains an image encoding and storage operator through which the digitized image file is stored in an attendant memory (framestore). Once stored in memory the digital image may be controllably modified or edited by resident image processing software, so that it may be appropriately formatted for reproduction by one or more devices the resolution of which may vary from device to device, such as a low/moderate NTSC television monitor or a very high resolution, digitally driven, thermal (laser) printer 16.
For optimum performance, it is necessary that the storage capacity of the framestore be at least as large as the spatial resolution of the highest resolution image to be processed. For example, if the highest resolution image capable of being accommodated is a 4096.times.3072 pixel array, the framestore may have a storage capacity on the order of twelve million addresses, corresponding to an address code resolution on the order of twenty four bits. To accommodate a highest resolution image, it has been customary practice to employ an addressing mechanism which preallocates framestore memory in segments of memory space on the basis of the (largest expected) number of pixels per line of such an image. Also, the dimensions of the image are allocated memory in powers of two of the number of pixels per line and lines per image array. Such a memory address preallocation scheme is diagrammatically illustrated in a simplified manner in FIG. 2.
More particularly, FIG. 2 shows a 4.times.3 pixel array 21 and a framestore 23, the storage capacity of which is twelve memory cells having respective addresses ADD#1-ADD#12. In the simplified example of FIG. 2, memory is preallocated in segments of four cells or memory addresses per line of pixels of the image, with memory addresses ADD#1-ADD#4 being preallocated to store the first line (pixels P1-P4), memory addresses ADD#5-ADD#8 preallocated to store the second line (pixels P5-P8), and memory addresses ADD#9-ADD#12 preallocated to store the third line (pixels P9-P12). Dotted lines are shown connecting respective pixel locations 1-12 of 4.times.3 pixel array 21 and respective memory addresses ADD#1-ADD#12 of memory 23, to illustrate the manner in which the pixel locations of the image matrix or array are assigned or preallocated to the memory. When the image is to be read out, the memory is scanned sequentially beginning with address ADD#1 and continuing though address ADD#12, so as to output the three lines of (four pixels per line of) the stored image.
To accommodate the not-infrequent case where the input image has a spatial resolution less than the capacity of the framestore, the conventional preallocation addressing scheme illustrated in FIG. 2 may employ a memory management scheme through which unused portions of memory or skipped, or it may cause unused portions of each memory segment to be filled or `stuffed` with prescribed data values, for example zeros. The effect of employing dummy fill data in association with the preallocation scheme of FIG. 2 on such a reduced spatial resolution image is diagrammatically illustrated in FIG. 3, which shows the manner in which a 3.times.2 pixel array 31 is mapped into framestore 23. For the reduced spatial resolution of 3.times.2 pixel array 31, since memory 23 is preallocated in four cell segments (i.e. four pixels per line segments), memory addresses ADD#1-ADD#3 will store the first line (pixels P1-P3) of the 3.times.2 image, but no imagery data is available for memory address ADD#4. In this case memory address ADD#4 is, in effect, a dummy memory cell, in which a prescribed data value (e.g. 0) may be written. For the next or second line of pixel data memory addresses ADD#5-ADD#7 store the data values of the second and last line of the image (pixels P4-P6) and memory address ADD#8 stores a zero, as do the remaining memory addresses ADD#9-ADD#12.
In will be appreciated that a preallocation scheme of the type diagrammatically illustrated in FIGS. 2 and 3 effectively performs a spatial mapping of an input image into the framestore such that the addressing mechanism accesses the entire memory. Not only does such an addressing scheme require additional processing complexity during the write cycle, but it is necessary to employ a mapping management tool to delete unwanted fill data on read-out. It can be seen therefore that this conventional technique of digital image storage suffers from increased hardware requirements, processing complexity and access time.